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Burst Transfer with a Slow Backend
Burst Transfer with a Slow Backend
Figure 6-10 to Figure 6-12 on page 61 show burst transfers with a backend that transfers one word of data every three
clock cycles. The PCI Master in this case is capable of transferring data every clock cycle. During these transfers, the
internal FIFO does not fill up, so the core keeps the RD_STB_OUT signal active, as it is ready to accept data. When
the backend asserts the RD_STB_IN signal, data is transferred to the core and then transferred on the PCI bus two
clock cycles later (three clock cycles for the SX-A and RTSX-S families).
cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
clk
framen
ad[31:0]
ADDR
0
1
2
3
cben[3:0]
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_stb_out
rd_stb_in
6
0
0
mem_add[15:0]
mem_data_in[31:0]
0000
0
0004
1
0008
2
000C
3
rd_sync
Figure 6-10 · Backend Burst Read Cycle with Slow Backend (RD_SYNC = 0)
v4.0
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